TTL.js Logic & IC Simulator
I/O
INPUT
OUTPUT
CLOCK
GATES
AND
OR
NOT
NAND
NOR
XOR
XNOR
BUFFER
FLIP-FLOPS
D-FF
JK-FF
SR-LATCH
T-FF
ICs
MUX 2:1
DEMUX 1:2
DECODER
MEMORY
RAM 4Γ—1
ROM 4Γ—1
BUS
BUS JOIN
BUS SPLIT